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| PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D Document Title 256Kx16 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. CMOS SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 History Initial release with Preliminary. Package dimension modify on page 11. Change Icc, Isb and Isb1 Item ICC(Commercial) 10ns 12ns 15ns 10ns 12ns 15ns Previous 90mA 80mA 70mA 115mA 100mA 85mA 30mA 10mA Current 65mA 55mA 45mA 85mA 75mA 65mA 20mA 5mA Draft Data September. 7. 2001 Septermber.28. 2001 November, 3, 2001 Remark Preliminary Preliminary Preliminary ICC(Industrial) ISB ISB1(Normal) Rev. 0.3 1. Correct AC parameters : Read & Write Cycle 2. Corrrect Power part : Delete "P-Industrial,Low Power" part 3. Delete Data Retention Characteristics 1. Delete 15ns speed bin. 2. Change Icc for Industrial mode. Item 10ns ICC(Industrial) 12ns 1. Final datasheet release. 2. Delete 12ns speed bin. 1. Add the Lead Free Package type. November, 23, 2001 Preliminary Rev. 0.4 December, 18, 2001 Previous 85mA 75mA Current 75mA 65mA July, 09, 2002 Preliminary Rev. 1.0 Final Rev. 2.0 June. 20, 2003 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D 4Mb Async. Fast SRAM Ordering Information Org. 1M x4 Part Number K6R4004C1D-J(K)C(I) 10 K6R4004V1D-J(K)C(I) 08/10 K6R4008C1D-J(K,T,U)C(I) 10 512K x8 K6R4008V1D-J(K,T,U)C(I) 08/10 K6R4016C1D-J(K,T,U,E)C(I) 10 256K x16 K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10 VDD(V) 5 3.3 5 3.3 5 3.3 Speed ( ns ) 10 8/10 10 8/10 10 8/10 PKG J : 32-SOJ K : 32-SOJ(LF) J : 36-SOJ K : 36-SOJ(LF) T : 44-TSOP2 U : 44-TSOP2(LF) J : 44-SOJ K : 44-SOJ(LF) T : 44-TSOP2 U: 44-TSOP2(LF) E : 48-TBGA CMOS SRAM Temp. & Power C : Commercial Temperature ,Normal Power Range I : Industrial Temperature ,Normal Power Range L : Commercial Temperature ,Low Power Range P : Industrial Temperature ,Low Power Range -2- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D 256K x 16 Bit High-Speed CMOS Static RAM FEATURES * Fast Access Time 10ns(Max.) * Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating K6R4016C1D-10 : 65mA(Max.) * Single 5.0V10% Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16 * Standard Pin Configuration K6R4016C1D-J : 44-SOJ-400 K6R4016C1D-K : 44-SOJ-400(Lead-Free) K6R4016C1D-T : 44-TSOP2-400BF K6R4016C1D-U : 44-TSOP2-400BF (Lead-Free) K6R4016C1D-E : 48-TBGA with 0.75 Ball pitch (7mm X 9mm) * Operating in Commercial and Industrial Temperature range. CMOS SRAM GENERAL DESCRIPTION The K6R4016C1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 262,144 words by 16 bits. The K6R4016C1D uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control(UB, LB). The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4016C1D is packaged in a 400mil 44-pin plastic SOJ or TSOP(II) forward or 48 T BGA. FUNCTIONAL BLOCK DIAGRAM Clk Gen. A0 A1 Pre-Charge Circuit Row Select A2 A3 A4 A5 A6 A7 A8 A9 I/O1~I/O 8 I/O9~I/O 16 Memory Array 1024 Rows 256 x 16 Columns Data Cont. Data Cont. Gen. CLK I/O Circuit & Column Select A10 A11 A12 A13 A 14 A 15 A16 A17 WE OE UB LB CS -3- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D PIN CONFIGURATION A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 1 2 3 4 5 6 7 8 9 CMOS SRAM (Top View) 1 2 3 4 5 6 4 4 A 17 4 3 A 16 4 2 A 15 4 1 OE 4 0 UB 3 9 LB 3 8 I/O 16 3 7 I/O 15 3 6 I/O 14 D Vss I/O4 A17 A7 I/O12 Vcc C I/O2 I/O3 A5 A6 I/O11 I/O10 B I/O1 UB A3 A4 CS I/O9 A LB OE A0 A1 A2 N.C I/O4 10 Vcc 11 Vss 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A5 18 A6 19 A7 20 A8 21 A9 22 SOJ/ TSOP2 3 5 I/O 13 3 4 Vss 3 3 Vcc 3 2 I/O 12 3 1 I/O 11 3 0 I/O 10 2 9 I/O 9 2 8 N.C 2 7 A 14 2 6 A 13 2 5 A 12 2 4 A 11 2 3 A 10 H N.C A8 A9 A10 A11 N.C G I/O8 N.C A12 A13 WE I/O16 F I/O7 I/O6 A14 A15 I/O14 I/O15 E Vcc I/O5 N.C A16 I/O13 Vss 48-TBGA PIN FUNCTION Pin Name A0 - A17 WE CS OE LB UB I/O1 ~ I/O 16 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Lower-byte Control(I/O 1~I/O 8) Upper-byte Control(I/O 9~I/O 16) Data Inputs/Outputs Power(+5.0V) Ground No Connection ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, V OUT VCC PD TSTG TA TA Rating -0.5 to V CC+0.5 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -4- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D RECOMMENDED DC OPERATING CONDITIONS* (TA=0 to 70C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5** Typ 5.0 0 Max 5.5 0 VCC+0.5*** 0.8 Unit V V V V CMOS SRAM * The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = V C C + 2.0V a.c (Pulse Width 8ns) for I 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=VSS to VCC CS = VIH or O E=VIH or WE=V IL VOUT=VSS to VCC Min. Cycle, 100% Duty CS = VIL, VIN=V I H or VIL, IOUT=0mA Min. Cycle, CS=V I H f=0MHz, CS V CC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA Com. Ind. 10ns 10ns Test Conditions Min -2 -2 2.4 Max 2 2 65 75 20 5 0.4 V V mA Unit A A mA Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance * Capacitance is sampled and not 100% tested. Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V TYP - Max 8 6 Unit pF pF -5- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.) TEST CONDITIONS* Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads * The above test conditions are also applied at industrial temperature range. CMOS SRAM Value 0V to 3V 3ns 1.5V See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V RL = 50 DOUT VL = 1.5V ZO = 50 30pF* 480 DOUT 255 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE* K6R4016C1D-10 Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD Min 10 3 0 0 0 3 0 - Max 10 10 5 5 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at industrial temperature range. -6- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D WRITE CYCLE* K6R4016C1D-10 CMOS SRAM Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(O E High) Write Pulse Width(O E Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 - Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at industrial temperature range. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS=OE=VIL, WE=VIH, UB, LB =VIL) tRC Address tOH Data Out Previous Valid Data tAA Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tBA UB, LB tBLZ(4,5) OE tOLZ Data out High-Z tHZ(3,4,5) CS tBHZ(3,4,5) tOHZ tOE tOH Valid Data tLZ(4,5) -7- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D NOTES (READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V or VOL OH levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) ( O E Clock) tWC Address tAW OE tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tOHZ(6) Data out Valid Data tDH High-Z tWP(2) tWR(5) TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed) tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z Valid Data tOW (10) (9) tWR(5) tWP1(2) tDH -8- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5) CMOS SRAM High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) TIMING WAVEFORM OF WRITE CYCLE(4) ( UB, L B Controlled) tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5) High-Z Valid Data tBLZ tWHZ(6) Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not . be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -9- Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D FUNCTIONAL DESCRIPTION CS H L L L WE X H X H OE X* H X L LB X X H L H L L L X L H L * X means Don t Care. CMOS SRAM I/O Pin I/O1~I/O8 X X H H L L H L L Write Read DOUT High-Z DOUT DIN High-Z DIN High-Z DOUT DOUT High-Z DIN DIN ICC ICC Not Select Output Disable High-Z High-Z I/O9~I/O16 High-Z High-Z ISB, ISB1 ICC UB Mode Supply Current - 10 Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D PACKAGE DIMENSIONS 44-SOJ-400 CMOS SRAM Units:millimeters/Inches #44 #23 11.18 0.12 0.440 0.005 10.1 6 0.40 0 9.40 0.25 0.370 0.010 0.20 +0.10 -0.05 0.008 +0.004 - 0.002 #1 28.98 MAX 1.141 25.58 0.12 1.125 0.005 ( 1.19 ) 0.047 3.76 1.27 MAX ( 0.050 ) 0.148 0.10 MAX 0.004 #22 0.69 MIN 0.027 ( 0.95 ) 0.0375 0.43 0.017 +0.10 -0.05 +0.004 - 0.002 1.27 0.050 0.71 +0.10 -0.05 0.028 +0.004 -0.002 44-TSOP2-400BF Units:millimeters/Inches 0~8 0.25 0.010 TYP #44 #23 0.45 ~0.75 0.018 ~ 0.030 1 0.1 6 0.400 11.76 0.20 0.463 0.008 ( 0.50 ) 0.020 #1 18.81 MAX 0.741 18.41 0.725 0.10 0.004 #22 0.075 0.125+ 0.035 - 0.005 +- 0.003 0.001 1.00 0.10 0.039 0.004 1.20 MAX 0.047 0.10 0.004 MAX ( 0.805 ) 0.032 0.30 +0.10 -0.05 0.012 + 0.004 - 0.002 0.80 0.0315 0.05 0.002 MIN - 11 Rev 2.0 June 2003 PRELIMPreliminaryPPPPPPPPPINARY K6R4016C1D PACKAGE DIMENSIONS Top View Bottom View CMOS SRAM Units : millimeter. B B 6 A #A1 B C C D 5 4 B1 3 2 1 0.50 A1 INDEX MARK 0.50 C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) Side View D C Min A B B1 C C1 D E E1 E2 Y 6.90 8.90 0.40 0.80 0.30 - Typ 0.75 7.00 3.75 9.00 5.25 0.45 0.90 0.55 0.35 - Max 7.10 9.10 0.50 1.00 0.40 0.08 - 12 Rev 2.0 June 2003 C 0.30 E1 E E2 |
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